In the fabrication of microelectronics components, a number of steps involved are polishing, especially surfaces for chemical-mechanical polishing for the purpose of recovering a selected material and/or planarizing the structure.
Accordingly, over the years, a number of vastly different types of polishing processes to remove material, sometimes in selective areas, have been developed and are utilized to varying degrees.
In many microelectronics applications a Si3N4 layer is deposited under a SiO2 layer to serve as a polish stop. The role of such polish stop is particularly important in Shallow Trench Isolation (STI) structures. Selectivity is characteristically expressed as the ratio of the oxide polish rate to the nitride polish rate. State of the art polishing slurries such as silica slurry at alkaline pH, or ceria slurry at neutral or alkaline pH have an oxide to nitride selectivity of about 3. Such ratio is not high enough for the nitride to adequately serve as a polish stop.
It could also therefore be desirable to provide a polishing procedure which achieved excellent removal of silicon dioxide along with exhorting an increased polishing selectivity rate as compared to silicon nitride.
Also in other microelectrics structures, a layer of silicon dioxide, silicon nitride and/or silicon oxynitride insulator is located beneath a metal layer such as a copper, tungsten or aluminum layer and a liner such as Ti, TiN, Ta and TaN to act as a polish stop. If the polishing rate selectivity of the metal to the underlying silicon dioxide, silicon nitride and/or silicon oxynitride can be increased, the liner might possibly be eliminated.
It could also therefore be desirable to provide a polishing procedure which achieves excellent removal of a metal along with exhibiting an increased polishing selectivity rate as compared to silicon dioxide, silicon nitride and/or silicon oxynitride.